As a device that can reconfigure a circuit logic configuration while logic circuit configuration information is input from the outside, a field programmable gate array: hereinafter referred to as “FPGA” is widely used. Furthermore, in order to reduce the circuit mount area by increasing an operating rate of the gate array as much as possible, in recent years, with the advanced research and development for a dynamically reconfigurable device, a demand for a high-speed reconfigurable device is being increased.
However, like the FPGA, with use of a configuration in which a gate array VLSI and a memory are separated from each other on different chips and the gate array VLSI and the memory are connected to each other via a metal wiring, it is difficult to realize a device where the reconfiguration can be performed at a high speed. For example, in the case where the operating frequency of the reconfigurable device is 100 MHz and the number of all the reconfiguration bits is 100,000 bits, if the reconfigurable device and an external memory are connected to each other via a single wiring, it is necessary to set the transfer speed to 10 Tbps. This transfer speed cannot be realized while the current standard CMOS process is used. Even when various revisions are made on the wiring, the number of usable connection pads in the package is limited to several thousand, and accordingly the speeding up has limitations. Therefore, it cannot be said that the electrical reconfiguration band the reconfigurable device is sufficiently high with respect to the reconfiguration bit number.
On the other hand, for example, processors capable performing the reconfiguration at a high speed such as a DAP/DNA (Digital Application Processor/Distributed Network Architecture) chip and a DRP (dynamically reconfigurable processor) are developed (refer to Non-patent Documents 11 and 12). Each of them is fabricated by packaging a reconfiguration memory and a micro processor on one chip. The reconfiguration memory inside the chip stores a reconfiguration context based on 3 to 16 banks. These banks are switched for each clock. This process is a so-called context switching method. An arithmetic and logic unit (ALU) of these devices can perform the reconfiguration for each clock at intervals of several nano seconds. However, these devices have disadvantages of an extreme difficulty of increasing the reconfiguration memory while the gate density is maintained.
In view of the above, to compensate these disadvantages, new devices are proposed and developed by combining various optical and electrical methods (refer to Non-patent Documents 7 to 10). Among those devices in particular, an optically reconfigurable gate array: hereinafter referred to as “ORGA” (refer to Patent Documents 1 and 2 and Non-patent Documents 1 to 3, and 6) and an optically differential reconfigurable gate array: hereinafter referred to as “ODRGA” (refer to Patent Document 3 and Non-patent Documents 4 and 5) are known which can shorten the reconfiguration time of the conventional FPGA. These devices are similar to the FPGA, but have a difference from the FPGA in that the reconfiguration on the gate array logic configuration is performed with use of optical signal input from an external optical memory. Hereinafter, similar to the ORGA and the ODRGA, devices that can perform the reconfiguration on the logic circuit with use of the optical signal input are generally referred to as “optically reconfigurable logic circuit”.
FIG. 18 shows a configuration of an optically reconfigurable logic circuit. An optically reconfigurable logic circuit 100 is composed of an optical part 101 and a VLSI area 102. The optical part 101 is provided with an optical system for irradiating the VLSI area 102 with an optical signal that contains logic circuit configuration information (refer to Patent Documents 1 to 5 and Non-patent Documents 1 to 5).
The optical part 101 is composed of an optical memory element such as a holographic memory or a spatial light modulator that stores the logic circuit configuration information and a light emitting element such as a laser or an LED for outputting irradiation light for reading the logic circuit configuration information from the optical memory element (refer to Patent Documents 2, 4, and 5 and Non-patent Document 2). With use of the light output from the light emitting element, the logic circuit configuration information is read out as an optical signal from the optical memory element.
Mounted to the VLSI area 102 are a configuration information input circuit provided with a light receiving element for detecting an optical signal input from the optical part 101, a logic configuration variable circuit for performing configuration on a logic structure on the basis on the logic circuit configuration information given by the optical signal input to the configuration input information input circuit, an input/output circuit for performing input and output of an external signal with respect to a logic configuration variable circuit, a controller for performing a control on the operation of the optically reconfigurable logic circuit 100 as a whole, and the like are mounted (refer to Patent Documents 1 to 3 and 5).
FIG. 19 shows an example of a configuration information input circuit in a conventional optically reconfigurable logic circuit (refer to Patent Document 3). FIG. 19 illustrates a configuration information input circuit used in an ODRGA.
This configuration information input circuit denoted by reference numeral 105 is provided with a photo diode D, a PMOS transistor M, and a T flip-flop (triggered flip-flop: hereinafter referred to as “TFF”). The photo diode D is subjected to reverse direction connection, and an anode is grounded. A cathode of the photo diode D is connected to a power source via the PMOS transistor M. The preset signal nPRESET is input to the gate of the PMOS transistor M (herein, symbol “n” represents a negative logic. In the drawings, the negative logic is indicated by an overline. The same holds true in the following description). The nPRESET is a negative logic, and when the nPRESET is 0, the cathode of the photo diode D is applied with a power source voltage Vc.
A common node N1 for the photo diode D and the PMOS transistor M is connected to a trigger input terminal nT of the TFF. A clock signal (CLOCK) is input to a clock terminal of the TFF, and a clear signal (nCLEAR) is input to a clear terminal nCLR of the TFF. The CLEAR is a negative logic signal. A 1-bit circuit configuration signal (CONFIG) is output from the output terminal Q of the TFF. The circuit configuration signal is a signal representing the logic circuit configuration information of the logic configuration variable circuit.
At the initial rise of CLOCK, when the input of the trigger input terminal nT is 1, the TFF reverses the logic value of the CONFIG, and when the input of the trigger input terminal nT is 0, the TFF keeps the logic value of the CONFIG. In addition, when the nCLEAR is 0, the TFF forcedly sets the CONFIG as 0.
A description will be given to the case in which the reconfiguration is performed on the logic configuration variable circuit.
(1) First of all, the nPRESET is set as 0, and after the power source voltage Vc is applied between the terminals of the photo diode D, the nPRESET is set as 1. As a result, due to a reversed bias junction capacitor of the photo diode D, the node N1 is set at an H level.
(2) Next, an optical signal is input from the optical part 101. Herein, when the photo diode D is irradiated with light, a current flows through the photo diode D. Therefore, a potential of the node N1 is set at an L level. When the photo diode D is not irradiated with light, the node N1 is kept at the H level.
(3) After the input of the optical signal from the optical part 101 is completed, at the initial rise of the CLOCK, when the node N1 is at the L level, the value of the CONFIG is kept, and when the node N1 is at the H level, the value of the CONFIG is reversed. As a result, the logic configuration switching of the logic configuration variable circuit is performed.
The above-mentioned operations (1) to (3) are hereinafter referred to as “refresh”.
The above-mentioned configuration is an example of a configuration information input circuit used in the ODRGA. When the configuration is used for the ORGA, instead of the TFF in FIG. 19, a D flip-flop, a latch, a memory, or the like is used.    [Patent Document 1]
Japanese Unexamined Patent Application Publication No. 2002-353317    [Patent Document 2]
U.S. Pat. No. 6,057,703    [Patent Document 3]
Japanese Unexamined Patent Application Publication No. 2004-064017    [Patent Document 4]
U.S. Pat. No. 6,222,755    [Patent Document 5]
U.S. Pat. No. 6,072,608    [Non-patent Document 1]
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Majd F. Sakr, Steven P. Levitan, C. Lee Giles, and Donald M. Chiarulli, “Reconfigurable processor employing optical channels”, Proceedings of the 1998 International Topical Meeting on Optics in Computing (OC'98), Proceedings of the SPIE, Vol. 3490, pp. 564-567, 1998.    [Non-patent Document 10]
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Hirotaka Nakano, Takeshi Shindo, Tetsuo Kazami, and Masato Motomura, “Development of Dynamically Reconfigurable Processor LSI”, NEC TECHNICAL JOURNAL, NEC Corporation, April 2003, Vol. 56, No. 4, pp. 99-102.    [Non-patent Document 12]
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